The invention relates to a buffer arrangement of a pulse code time multiplex (PCM) exchange system for compensating both short and long term phase drift of information between a first and a second data path. The first data path may be a PCM time multiplex transmission line for transmitting information to a receiving unit of a PCM time multiplex exchange system, wherein such data transmission is controlled by a first (external) clock. The second data path may be an internal data path connected to the receiving unit of the exchange system. This unit and the second data path are controlled by a second (internal) clock. In theory, the two different clock pulse trains have to be exactly synchronized to achieve a synchronous mode of operation. In practice, such characteristics cannot be obtained with reasonable effort, and a plesiochronous mode of operation has to be taken into consideration. In this mode of operation, a phase drift and even a frequency drift between both clocks have to be acknowledged. If even the frequencies of both clocks do not differ from each other, the phase relationship between individual incoming PCM signals and corresponding conditions of the exchange system unit change steadily.
As well known, the influence of such phase drift can be eliminated to some extent by buffering information at an interface between both data paths. Incoming PCM signals are stored in a buffer storage at the rate of the external clock and are read out to the second data path at the rate of the internal clock. Transmitted information thus is aligned to the time pattern of the exchange system unit.
Because of the limited storage capacity of any such buffer storage, at least in case of a long term frequency shift between the external and the internal clock, after some time a phase correction has to be performed resulting in a loss of information which has to be tolerated. This is true for frequency differences in both directions. A higher frequency of the external clock leads to storing of more pieces of information than are read out during one and the same time span. The difference in position between pieces of information being currently buffered and those which are read out decreases correspondingly. As soon as a writing operation into the storage buffer is about to intersect a reading operation from the same storage location, transmitted information has to be skipped to avoid such colliding buffer operations.
If the frequency difference between the external clock and the internal clock constantly has a negative value, i.e. reading is performed faster than writing, the offset in position increases to an extent which finally also may cause an interception. An address jump for reading operations is performed which results in reading buffered pieces of information a second time, thereby re-establishing the theoretical optimum of the phase shift. In both cases, a loss of information occurs, either by surpassing information or by transmitting pieces of information a second time.
According to the basic theory of pulse code modulation (PCM) such information loss is not of serious concern as long as the sampling frequency is high enough compared to the maximum frequency of the original analog signal. With sophisticated PCM time multiplex exchange systems, however, a loss of pieces of information becomes more serious. Presently known PCM exchange systems, for example, make use of a method of grouping channels which is known as justification or stuffing method. According to this method, a train of coded pulses is transmitted in the form of PCM words wherein specific bit positions are reserved for synchronizing purposes, rather than being used for carrying analog signal information. These synchronizing bits are often also designated as stuffing or justifying digits, and are split off at a receiving station for reproducing the original time pattern. Especially in wide spread telecommunication systems several transmission lines may be linked together for transmitting information and the phase drifts of the individual lines accumulate to an extent which is critical, if such self-synchronizing methods are used.
Therefore, corrections of phase drift in a buffer storage have to be executed such that they do not interfere with a specific order of PCM words in a frame containing time and/or space multiplexed PCM words of a group of analog channels. This is of importance especially if wide band information is transmitted within one pulse frame and an undetermined number of time channels could be lost by a slip operation. The alignment of channels to each other within one pulse frame would be disturbed and could not be reproduced without unreasonable effort.
In German Pat. No. 2,641,488 there is disclosed a conventional solution for this object by means of a circuit arrangement for compensating phase drift of information transfers. There is provided a buffer arrangement consisting of an intermediate storage device and a buffer storage. The intermediate storage device has a storage capacity which is supposed to be sufficient for compensating even a maximum of phase jitter of the first clock. The intermediate storage device buffers eight PCM words and respective parts of time channel addresses for identifying the stored PCM words within a PCM frame. In any case when subsequent neighboring storage locations of the intermediate storage device are selected for a reading and a writing operation a special mode of operation at a higher frequency is initiated.
If the frequency of the first clock is higher than the frequency of the second clock, the intermediate storage device is read out twice as fast as normal. In case of a higher second clock frequency the same storage location of the intermediate storage device is read out several times.
If a series of special mode operations has to be performed because of a long term discrepancy of the clock frequencies, the buffer storage designed for buffering PCM words of an entire pulse frame will not be able to catch up or to balance these accumulating corrections. In such a case, also, a correction operation at the buffer storage is performed to avoid interfering of read and write operations at the same buffer location. According to the characteristic of the known circuit arrangement, any correction is to be accomplished at the time when the first PCM word of a pulse frame is read out, thus avoiding a complicated re-assignment or re-alignment of time channels within a pulse frame. This is achieved by controlling the operation of the intermediate storage device such that the starting time of a correction operation as described herein before coincides with a time slot of the time pattern of a pulse frame assigned to a specific time channel. This starting time determines the series of correction operations to be completed at a moment suitable for performing a subsequent correction operation at the buffer storage, if necessary.
The operation of the known buffer arrangement thus depends upon a variety of inference factors requiring a complicated monitoring and controlling system and still has some restrictions with respect to the amount of frequency drift which is manageable by the exchange system.
It is, therefore, a general object of the present invention to provide an improved pulse code time and/or space multiplex exchange system having a higher phase drift tolerance characteristic.
Another object of the present invention is to provide a buffer arrangement in such an exchange system for aligning the transmission of PCM signals from a first data path to a second data path independent from monitoring the starting point or the occurrence of specific channels of a pulse frame.
Still another object of the present invention is to provide a buffer arrangement as set forth herein before, with less complicated control logic than with conventional buffer arrangements.
These objects and other and further objects will become more apparent to those skilled in the art from the following description with reference to the drawings.